71 search results - page 11 / 15 » Parameterized Memory Models and Concurrent Separation Logic |
143
Voted
SIAMCOMP
1998
15 years 3 months ago
1998
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
122
Voted
IFIP
2004
Springer
15 years 9 months ago
2004
Springer
We introduce a new synchronization problem in mobile ad-hoc systems: the Driving Philosophers. In this problem, an unbounded number of driving philosophers (processes) access a rou...
123
Voted
IGPL
2010
15 years 2 months ago
2010
Researchers studying complex cognition have grown increasingly interested in mapping symbolic cognitive architectures onto subsymbolic brain models. Such a mapping seems essential...
142
Voted
IEEEPACT
2006
IEEE
15 years 9 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
178
Voted
SIGOPS
2010
14 years 10 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...