187 search results - page 21 / 38 » Parametric Encryption Hardware Design |
AES
2000
Springer
15 years 2 months ago
2000
Springer
The National Institute of Standards and Technology (NIST) has announced that one of the design criteria for the Advanced Encryption Standard (AES) algorithm was the ability to eļ¬...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then ...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
AbstractāMultiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
ICES
2007
Springer
14 years 11 months ago
2007
Springer
Combinational multipliers represent a class of circuits that is usually considered to be hard to design by means of the evolutionary techniques. However, experiments conducted unde...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a signiļ¬cant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...