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» Parametric Encryption Hardware Design
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EH
2000
IEEE
156views Hardware» more  EH 2000»
15 years 2 months ago
Evolution of Analog Circuits on Field Programmable Transistor Arrays
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
Adrian Stoica, Didier Keymeulen, Ricardo Salem Zeb...
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
15 years 1 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
15 years 1 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
TII
2010
146views Education» more  TII 2010»
14 years 4 months ago
A Flexible Design Flow for Software IP Binding in FPGA
Software intellectual property (SWIP) is a critical component of increasingly complex field programmable gate arrays (FPGA)-based system-on-chip (SOC) designs. As a result, develop...
Michael A. Gora, Abhranil Maiti, Patrick Schaumont
87
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ASPDAC
2001
ACM
112views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Parameterized MAC unit implementation
Ethernet communication devices, such as adapter, hub, bridge and switch, all follow IEEE 802.3 standard protocol. We have designed and implemented an integrated 10/100 Mbps Etherne...
Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen