Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
e Abstraction Arie Gurfinkel1 , Ou Wei2 , and Marsha Chechik2 1 Software Engineering Institute, Carnegie Mellon University 2 Department of Computer Science, University of Toronto A...