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» Parametric Encryption Hardware Design
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FPL
2010
Springer
170views Hardware» more  FPL 2010»
14 years 7 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
MSE
2003
IEEE
104views Hardware» more  MSE 2003»
15 years 2 months ago
Internet-based Tool for System-on-Chip Integration
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...
David Lim, Christopher E. Neely, Christopher K. Zu...
FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 2 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
MSS
2007
IEEE
86views Hardware» more  MSS 2007»
15 years 3 months ago
RAIF: Redundant Array of Independent Filesystems
Storage virtualization and data management are well known problems for individual users as well as large organizations. Existing storage-virtualization systems either do not suppo...
Nikolai Joukov, Arun M. Krishnakumar, Chaitanya Pa...
EIT
2008
IEEE
14 years 11 months ago
Experiments in attacking FPGA-based embedded systems using differential power analysis
Abstract--In the decade since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer securit...
Song Sun, Zijun Yan, Joseph Zambreno