149 search results - page 14 / 30 » Parametric Fault Simulation and Test Vector Generation |
ATS
2004
IEEE
15 years 1 months ago
2004
IEEE
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of rev...
73
Voted
ATS
2003
IEEE
15 years 2 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
ITC
2003
IEEE
15 years 2 months ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
ICES
2000
Springer
15 years 1 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
77
Voted
ITC
2003
IEEE
15 years 2 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...