3738 search results - page 512 / 748 » Parametrized Logic Programming |
118
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SIGSOFT
2003
ACM
15 years 6 months ago
2003
ACM
Model checking is an automated technique for verifying that a system satisfies a set of required properties. Such properties are typically expressed as temporal logic formulas, in...
FPL
2009
Springer
15 years 5 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
125
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CSFW
1999
IEEE
15 years 5 months ago
1999
IEEE
Most formal approaches to security protocol analysis are based on a set of assumptions commonly referred to as the "Dolev-Yao model." In this paper, we use a multiset re...
104
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FPGA
1997
ACM
15 years 4 months ago
1997
ACM
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
92
Voted
ISAAC
1992
Springer
15 years 4 months ago
1992
Springer
In the multilevel generalized assignment problem (MGAP) agents can perform tasks at more than one efficiency level. Important manufacturing problems, such as lot sizing, can be ea...