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» Parametrized Logic Programming
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VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 1 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
121
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ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
15 years 9 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
106
Voted
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
15 years 5 months ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
119
Voted
SAC
2002
ACM
15 years 7 days ago
Option pricing under model and parameter uncertainty using predictive densities
The theoretical price of a financial option is given by the expectation of its discounted expiry time payoff. The computation of this expectation depends on the density of the val...
F. Oliver Bunnin, Yike Guo, Yuhe Ren
95
Voted
FASE
2010
Springer
15 years 7 months ago
A Lightweight and Portable Approach to Making Concurrent Failures Reproducible
Multithreaded concurrent programs often exhibit bugs due to unintended interferences among the concurrent threads. Such bugs are often hard to reproduce because they typically hap...
Qingzhou Luo, Sai Zhang, Jianjun Zhao, Min Hu