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» Partial Order Reduction for Model Checking of Timed Automata
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DATE
2004
IEEE
184views Hardware» more  DATE 2004»
15 years 1 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
KBSE
2007
IEEE
15 years 3 months ago
Testing concurrent programs using value schedules
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...
Jun Chen, Steve MacDonald
WOSP
2005
ACM
15 years 3 months ago
A model transformation framework for the automated building of performance models from UML models
In order to effectively validate the performance of software systems throughout their development cycle it is necessary to continuously build performance models from software mod...
Andrea D'Ambrogio
FMICS
2007
Springer
15 years 3 months ago
An Approach to Formalization and Analysis of Message Passing Libraries
Message passing using libraries implementing the Message Passing Interface (MPI) standard is the dominant communication mechanism in high performance computing (HPC) applications. ...
Robert Palmer, Michael Delisi, Ganesh Gopalakrishn...
ENTCS
2006
109views more  ENTCS 2006»
14 years 9 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...