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ITC
2003
IEEE
141views Hardware» more  ITC 2003»
15 years 9 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba
135
Voted
IPPS
2000
IEEE
15 years 9 months ago
Ordering Unstructured Meshes for Sparse Matrix Computations on Leading Parallel Systems
Abstract. Computer simulations of realistic applications usually require solving a set of non-linear partial di erential equations PDEs over a nite region. The process of obtaini...
Leonid Oliker, Xiaoye S. Li, Gerd Heber, Rupak Bis...
RTCSA
1998
IEEE
15 years 8 months ago
Protocol Synthesis from Context-Free Processes Using Event Structures
In this paper, we propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique n...
Akio Nakata, Teruo Higashino, Kenichi Taniguchi
CONCUR
1992
Springer
15 years 8 months ago
The Duality of TIme and Information
The states of a computing system bear information and change time, while its events bear time and change information. We develop a primitive algebraic model of this duality of tim...
Vaughan R. Pratt
LICS
1991
IEEE
15 years 8 months ago
Defaults and Revision in Structured Theories
Starting from a logic which speci es how to make deductions from a set of sentences (a ` at theory'), a way to generalise this toa partiallyordered bag ofsentences (a `struct...
Mark Ryan