58 search results - page 11 / 12 » Partial and Dynamically Reconfiguration of Xilinx Virtex-II ... |
116
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CODES
2009
IEEE
15 years 5 months ago
2009
IEEE
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
106
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DAC
2002
ACM
16 years 2 months ago
2002
ACM
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
126
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CSREAESA
2009
15 years 3 months ago
2009
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
106
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RECONFIG
2009
IEEE
15 years 8 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
134
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IPPS
2005
IEEE
15 years 7 months ago
2005
IEEE
Data flow and FSMs are used intensively to specify real-time systems in the field of mechatronics. Their implementation in FPGAs is discussed against the background of dynamic rec...