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IJES
2006
93views more  IJES 2006»
14 years 9 months ago
Dynamically configurable security for SRAM FPGA bitstreams
This paper proposes a solution to improve the security of SRAM FPGAs through bitstream encryption. This proposition is distinct from other works because it uses the latest capabil...
Lilian Bossuet, Guy Gogniat, Wayne Burleson
ERSA
2010
186views Hardware» more  ERSA 2010»
14 years 7 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
CSREAESA
2006
14 years 11 months ago
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs
Abstract
Daniel T. Milton, Sachin Dhingra, Charles E. Strou...
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
15 years 1 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
FCCM
1997
IEEE
111views VLSI» more  FCCM 1997»
15 years 1 months ago
Real-time stereo vision on the PARTS reconfigurable computer
This paper describes a powerful, scalable, reconfigurable computer called the PARTS engine. The PARTS engine consists of 16 Xilinx 4025 FPGAs, and 16 one-megabyte SRAMs. The FPGAs...
John Woodfill, Brian Von Herzen