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CODES
2006
IEEE
15 years 6 months ago
Retargetable code optimization with SIMD instructions
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...
85
Voted
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 6 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
GLOBECOM
2006
IEEE
15 years 6 months ago
Relay Selection in Multi-Node Cooperative Communications: When to Cooperate and Whom to Cooperate with?
Abstract— In this paper, we propose a new cooperative communication protocol, which achieves high bandwidth efficiency while guaranteeing full diversity order. The proposed sche...
Ahmed S. Ibrahim, Ahmed K. Sadek, Weifeng Su, K. J...
IPPS
2006
IEEE
15 years 6 months ago
An adaptive system-on-chip for network applications
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik...
69
Voted
ISCA
2006
IEEE
158views Hardware» more  ISCA 2006»
15 years 6 months ago
Memory Model = Instruction Reordering + Store Atomicity
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
Arvind, Jan-Willem Maessen