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» Partitionability of the Multistage Interconnection Networks
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GLOBECOM
2006
IEEE
14 years 8 days ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
HOTI
2008
IEEE
14 years 21 days ago
Adaptive Routing Strategies for Modern High Performance Networks
Today’s scalable high-performance applications heavily depend on the bandwidth characteristics of their communication patterns. Contemporary multi-stage interconnection networks...
Patrick Geoffray, Torsten Hoefler
IPPS
1998
IEEE
13 years 10 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
IPPS
2006
IEEE
14 years 8 days ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
14 years 17 days ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...