338 search results - page 22 / 68 » Partitioning of VLSI Circuits and Systems |
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
GECCO
2003
Springer
15 years 2 months ago
2003
Springer
Abstract. In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local op...
ICCD
1999
IEEE
15 years 1 months ago
1999
IEEE
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
99
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GLVLSI
2010
IEEE
14 years 9 months ago
2010
IEEE
The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Mac...
102
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JGT
2007
14 years 9 months ago
2007
A transition system T of an Eulerian graph G is a family of partitions of the edges incident to each vertex of G into transitions i.e. subsets of size two. A circuit decomposition...