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» Partitioning of VLSI Circuits and Systems
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DFT
1999
IEEE
131views VLSI» more  DFT 1999»
15 years 2 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
DAC
1998
ACM
15 years 10 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
GLVLSI
2003
IEEE
122views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Cooling of integrated circuits using droplet-based microfluidics
Decreasing feature sizes and increasing package densities are making thermal issues extremely important in IC design. Uneven thermal maps and hot spots in ICs cause physical stres...
Vamsee K. Pamula, Krishnendu Chakrabarty
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Reliability-Aware SOC Voltage Islands Partition and Floorplan
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
15 years 3 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...