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» Partitioning of VLSI Circuits and Systems
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89
Voted
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
15 years 10 months ago
A Design of Analog C-Matrix Circuits Used for Signal/Data Processing
Various calculation of matrices and vectors has been used in many digital signal processing systems. Although the calculation simply repeats multiplication and addition, the reite...
Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yo...
72
Voted
DAC
2005
ACM
14 years 11 months ago
Faster and better global placement by a new transportation algorithm
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Ulrich Brenner, Markus Struzyna
HIPC
2005
Springer
15 years 3 months ago
The Potential of On-Chip Multiprocessing for QCD Machines
We explore the opportunities offered by current and forthcoming VLSI technologies to on-chip multiprocessing for Quantum Chromo Dynamics (QCD), a computational grand challenge for ...
Gianfranco Bilardi, Andrea Pietracaprina, Geppino ...
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
15 years 1 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag