Sciweavers

338 search results - page 32 / 68
» Partitioning of VLSI Circuits and Systems
Sort
View
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
15 years 3 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
15 years 2 months ago
Benchmarking for large-scale placement and beyond
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
15 years 4 months ago
Multiple-Width Bus Partitioning Approach to Datapath Synthesis
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
Arash Ahmadi, Mark Zwolinski
GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh
FMCAD
2007
Springer
15 years 1 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet