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» Partitioning of VLSI Circuits and Systems
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73
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ASYNC
1998
IEEE
110views Hardware» more  ASYNC 1998»
15 years 1 months ago
Analyzing Specifications for Delay-Insensitive Circuits
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays inc...
Tom Verhoeff
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
15 years 3 months ago
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics
As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the c...
Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
15 years 10 months ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
82
Voted
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
15 years 3 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker