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» Partitioning of VLSI Circuits and Systems
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VLSI
2010
Springer
14 years 4 months ago
Spatial EM jamming: A countermeasure against EM Analysis?
Electro-Magnetic Analysis has been identified as an efficient technique to retrieve the secret key of cryptographic algorithms. Although similar mathematically speaking, Power or E...
Francois Poucheret, Lyonel Barthe, Pascal Benoit, ...
ISPD
2003
ACM
89views Hardware» more  ISPD 2003»
15 years 2 months ago
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
Andrew B. Kahng, Xu Xu
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
15 years 3 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
DAC
2006
ACM
15 years 10 months ago
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
Hao Hua, Christopher Mineo, Kory Schoenfliess, Amb...
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra