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» Partitioning of VLSI Circuits and Systems
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ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
15 years 3 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
15 years 1 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 1 months ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
89
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ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
15 years 6 months ago
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
Zhuo Feng, Peng Li
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
15 years 2 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...