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» Partitioning of VLSI Circuits and Systems
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ASPDAC
1998
ACM
74views Hardware» more  ASPDAC 1998»
15 years 1 months ago
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines
— Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus li...
Hiroshi Kawaguchi, Takayasu Sakurai

Publication
576views
16 years 9 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
74
Voted
SBCCI
2009
ACM
131views VLSI» more  SBCCI 2009»
15 years 2 months ago
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
Hagen Sämrow, Claas Cornelius, Frank Sill, An...
DAC
2005
ACM
15 years 10 months ago
A lattice-based framework for the classification and design of asynchronous pipelines
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Peggy B. McGee, Steven M. Nowick
VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
15 years 10 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...