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» Partitions of an Integer into Powers
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ICCAD
2007
IEEE
100views Hardware» more  ICCAD 2007»
15 years 6 months ago
Parallel domain decomposition for simulation of large-scale power grids
This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-ov...
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. So...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 5 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 6 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
15 years 4 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 8 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal