This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-ov...
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. So...
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...