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ANCS
2009
ACM
14 years 9 months ago
Weighted random oblivious routing on torus networks
Torus, mesh, and flattened butterfly networks have all been considered as candidate architectures for on-chip interconnection networks. In this paper, we study the problem of opti...
Rohit Sunkam Ramanujam, Bill Lin
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
15 years 8 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
SC
2009
ACM
15 years 6 months ago
Implementing sparse matrix-vector multiplication on throughput-oriented processors
Sparse matrix-vector multiplication (SpMV) is of singular importance in sparse linear algebra. In contrast to the uniform regularity of dense linear algebra, sparse operations enc...
Nathan Bell, Michael Garland
ICC
2009
IEEE
122views Communications» more  ICC 2009»
15 years 6 months ago
A Partial-Protection Approach Using Multipath Provisioning
—We study the problem of reliably provisioning traffic using multipath routing in a mesh network. Traditional approaches handled reliability requirements using full-protection s...
Ananya Das, Charles U. Martel, Biswanath Mukherjee
IEEEPACT
2009
IEEE
15 years 6 months ago
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
—Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-...
Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel...