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IPPS
2005
IEEE
15 years 10 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
15 years 10 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
MSS
2005
IEEE
64views Hardware» more  MSS 2005»
15 years 10 months ago
STORAGEDB: Enhancing the Storage Sub-System with DBMS Functionalities
This paper proposes STORAGEDB: a paradigm for implementing storage virtualation using databases. It describes details for storing the logical-to-physical mapping information as ta...
Lin Qiao, Balakrishna R. Iyer, Divyakant Agrawal, ...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
15 years 10 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
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SEUS
2005
IEEE
15 years 10 months ago
Measurement-Based Worst-Case Execution Time Analysis
In the last years the number of electronic control systems has increased significantly. In order to stay competitive more and more functionality is integrated into more and more p...
Ingomar Wenzel, Raimund Kirner, Bernhard Rieder, P...