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» Path delay test compaction with process variation tolerance
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GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
13 years 11 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
14 years 22 days ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...
ICCAD
2006
IEEE
130views Hardware» more  ICCAD 2006»
14 years 3 months ago
On bounding the delay of a critical path
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
Leonard Lee, Li-C. Wang
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
14 years 23 days ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 3 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...