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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 7 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
ASPLOS
1992
ACM
15 years 7 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
122
Voted
ASPLOS
2006
ACM
15 years 6 months ago
Accurate and efficient filtering for the Intel thread checker race detector
Debugging data races in parallel applications is a difficult task. Error-causing data races may appear to vanish due to changes in an application's optimization level, thread...
Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Peter...
JAVA
2000
Springer
15 years 6 months ago
Bulk file I/O extensions to Java
The file I/O classes present in Java have proven too inefficient to meet the demands of high-performance applications that perform large amounts of I/O. The inefficiencies stem pr...
Dan Bonachea
ASPLOS
2008
ACM
15 years 5 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen