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    SBACPAD
    2008
    IEEE
    170views Hardware» more  SBACPAD 2008»
    Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
    15 years 4 months ago
    Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
    Download  www.ideal.ece.ufl.edu
    Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
    James Poe, Chang-Burm Cho, Tao Li
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    ASAP
    2007
    IEEE
    111views Hardware» more  ASAP 2007»
    Entropy Coding on a Programmable Processor Array for Multimedia SoC
    15 years 4 months ago
    Entropy Coding on a Programmable Processor Array for Multimedia SoC
    Download  www.ac.usc.es
    Entropy encoding and decoding is a crucial part of any multimedia system that can be highly demanding in terms of computing power. Hardware implementation of typical compression a...
    Roberto R. Osorio, Javier D. Bruguera
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    ASAP
    2007
    IEEE
    135views Hardware» more  ASAP 2007»
    An Application Specific Memory Characterization Technique for Co-processor Accelerators
    15 years 4 months ago
    An Application Specific Memory Characterization Technique for Co-processor Accelerators
    Download  ft.ornl.gov
    Commodity accelerator technologies including reconfigurable devices provide an order of magnitude performance improvement compared to mainstream microprocessor systems. A number o...
    Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith
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    DSN
    2007
    IEEE
    224views Computer Networks» more  DSN 2007»
    Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
    15 years 4 months ago
    Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
    Download  www.eecs.harvard.edu
    Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
    Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
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    ICMCS
    2007
    IEEE
    144views Multimedia» more  ICMCS 2007»
    A Framework for Modular Signal Processing Systems with High-Performance Requirements
    15 years 4 months ago
    A Framework for Modular Signal Processing Systems with High-Performance Requirements
    Download  www.nist.gov
    This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
    Lukas Diduch, Ronald Müller, Gerhard Rigoll
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