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DATE
2002
IEEE
89views Hardware» more  DATE 2002»
15 years 4 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
15 years 6 months ago
Enrichment of limited training sets in machine-learning-based analog/RF test
Abstract— This paper discusses the generation of informationrich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of ...
Haralampos-G. D. Stratigopoulos, Salvador Mir, Yio...
TVLSI
2008
133views more  TVLSI 2008»
14 years 11 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
ISSRE
2003
IEEE
15 years 5 months ago
An Empirical Study on Testing and Fault Tolerance for Software Reliability Engineering
Software testing and software fault tolerance are two major techniques for developing reliable software systems, yet limited empirical data are available in the literature to eval...
Michael R. Lyu, Zubin Huang, Sam K. S. Sze, Xia Ca...
ISSRE
2003
IEEE
15 years 5 months ago
Augmenting Simulated Annealing to Build Interaction Test Suites
Component based software development is prone to unexpected interaction faults. The goal is to test as many potential interactions as is feasible within time and budget constraint...
Myra B. Cohen, Charles J. Colbourn, Alan C. H. Lin...