5799 search results - page 1122 / 1160 » Patterns Generate Architectures |
ICCAD
2005
IEEE
15 years 9 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
110
Voted
CGO
2010
IEEE
15 years 7 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
99
Voted
MSWIM
2009
ACM
15 years 7 months ago
2009
ACM
It is common practice in wireless multihop network evaluations to ignore interfering signals below a certain signal strength threshold. This paper investigates the thesis that thi...
95
Voted
ICS
2009
Tsinghua U.
15 years 7 months ago
2009
Tsinghua U.
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
116
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LCTRTS
2009
Springer
15 years 7 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...