Sciweavers

5799 search results - page 292 / 1160
» Patterns Generate Architectures
Sort
View
95
Voted
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 10 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
IWSOC
2003
IEEE
99views Hardware» more  IWSOC 2003»
15 years 10 months ago
Template Generation and Selection Algorithms
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Pa...
FPL
2009
Springer
85views Hardware» more  FPL 2009»
15 years 9 months ago
Generating high-performance custom floating-point pipelines
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
Florent de Dinechin, Cristian Klein, Bogdan Pasca
KBSE
2000
IEEE
15 years 9 months ago
Systematic Generation of Dependable Change Coordination Plans for Automated Switching of Coordination Policies
Distributed information systems for decision support and e-commerce applications require coordination of multiple autonomous components and their services to accomplish a set of g...
Prasanta K. Bose, Mark G. Matthews
IADIS
2003
15 years 6 months ago
Service Capabilities Model for Next Generation Ad Hoc Networks
Next generation networks are commonly associated with open service creation environments such as OSA, Parlay or JAIN. These environments make the capabilities provided by telecomm...
Mario Muñoz