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135
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ATS
2005
IEEE
98views Hardware» more  ATS 2005»
15 years 9 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
133
Voted
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 9 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski
143
Voted
DSN
2005
IEEE
15 years 9 months ago
Reversible Fault-Tolerant Logic
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
P. Oscar Boykin, Vwani P. Roychowdhury
128
Voted
ECRTS
2005
IEEE
15 years 9 months ago
A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems
Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average,...
François Bodin, Isabelle Puaut
FDL
2005
IEEE
15 years 9 months ago
Embed Scripting inside SystemC
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as Sy...
J. Vennin, S. Penain, Luc Charest, Samy Meftali, J...