6750 search results - page 11 / 1350 » Performance Analysis Framework for Layout Analysis Methods |
DDECS
2007
IEEE
15 years 4 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ISPD
1998
ACM
15 years 1 months ago
1998
ACM
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
RIAO
2000
14 years 11 months ago
2000
We present a framework to analyze color documents of complex layout. In addition, no assumption is made on the layout. Our framework combines in a content-driven bottom-up approac...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...