6750 search results - page 13 / 1350 » Performance Analysis Framework for Layout Analysis Methods |
72
Voted
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ICIP
2003
IEEE
15 years 11 months ago
2003
IEEE
Due to attenuation and spatial smoothing that occurs in the conducting media, the bioelectric inverse problem of estimating sources from remote measurements is ill-posed and solut...
WORDS
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper presents a method to analyze the timing behavior of an event-based real-time protocol composition framework. The framework, called RT-Appia, allows the development and ...
TCAD
1998
14 years 9 months ago
1998
— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
— Traffic shaping is a well-known technique in the area of networking and is proven to reduce global buffer requirements and end-to-end delays in networked systems. Due to these...