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IPPS
2003
IEEE
15 years 8 months ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu
CASES
2008
ACM
15 years 5 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ECMDAFA
2010
Springer
228views Hardware» more  ECMDAFA 2010»
15 years 6 months ago
Example-Based Sequence Diagrams to Colored Petri Nets Transformation Using Heuristic Search
Dynamic UML models like sequence diagrams (SD) lack sufficient formal semantics, making it difficult to build automated tools for their analysis, simulation and validation. A commo...
Marouane Kessentini, Arbi Bouchoucha, Houari A. Sa...
CCS
2011
ACM
14 years 3 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 6 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang