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94
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MOMPES
2008
IEEE
15 years 7 months ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
Dionisio de Niz
95
Voted
RE
2008
Springer
15 years 2 days ago
Examining the Relationships between Performance Requirements and "Not a Problem" Defect Reports
Missing or imprecise requirements can lead stakeholders to make incorrect assumptions. A "Not a Problem" defect report (NaP) describes a software behavior that a stakeho...
Chih-Wei Ho, Laurie Williams, Brian Robinson
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
15 years 4 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
93
Voted
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 6 months ago
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
94
Voted
EMSOFT
2007
Springer
15 years 6 months ago
Optimal task placement to improve cache performance
Most recent embedded systems use caches to improve their average performance. Current timing analyses are able to compute safe timing guarantees for these systems, if tasks are ru...
Gernot Gebhard, Sebastian Altmeyer