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ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
15 years 7 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
CVPR
2009
IEEE
1724views Computer Vision» more  CVPR 2009»
16 years 9 months ago
Optimal Single Image Capture for Motion Deblurring
Deblurring images of moving objects captured from a traditional camera is an ill-posed problem due to the loss of high spatial frequencies in the captured images. Recent techniques...
Amit K. Agrawal, Ramesh Raskar
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 8 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
IPPS
2006
IEEE
15 years 8 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 7 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...