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» Performance Evaluation of Memory Caches in Multiprocessors
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LCTRTS
2010
Springer
15 years 4 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
ASPLOS
2006
ACM
15 years 1 months ago
Efficiently exploring architectural design spaces via predictive modeling
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R...
SPAA
2006
ACM
15 years 3 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
SIGMOD
2000
ACM
158views Database» more  SIGMOD 2000»
15 years 1 months ago
NiagaraCQ: A Scalable Continuous Query System for Internet Databases
Continuous queries are persistent queries that allow users to receive new results when they become available. While continuous query systems can transform a passive web into an ac...
Jianjun Chen, David J. DeWitt, Feng Tian, Yuan Wan...
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 3 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...