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HPCA
2005
IEEE
15 years 5 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
IPPS
1998
IEEE
15 years 3 months ago
Comparing the Optimal Performance of Different MIMD Multiprocessor Architectures
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...
Lars Lundberg, Håkan Lennerstad
ASPLOS
2010
ACM
15 years 5 months ago
Probabilistic job symbiosis modeling for SMT processor scheduling
Symbiotic job scheduling boosts simultaneous multithreading (SMT) processor performance by co-scheduling jobs that have ‘compatible’ demands on the processor’s shared resour...
Stijn Eyerman, Lieven Eeckhout
GCC
2004
Springer
15 years 5 months ago
XML Based X.509 Authorization in CERNET Grid
: This paper presents an authorization solution for resource management and control developing as a part of the China Education and Research Network (CERNET) to perform fine-graine...
Wu Liu, Jianping Wu, Hai-Xin Duan, Xing Li, Ping R...
GECCO
2009
Springer
162views Optimization» more  GECCO 2009»
14 years 9 months ago
Uncertainty handling CMA-ES for reinforcement learning
The covariance matrix adaptation evolution strategy (CMAES) has proven to be a powerful method for reinforcement learning (RL). Recently, the CMA-ES has been augmented with an ada...
Verena Heidrich-Meisner, Christian Igel