45 search results - page 3 / 9 » Performance Evaluation of Tiling for the Register Level |
LCTRTS
2007
Springer
15 years 4 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
ISCA
1995
IEEE
15 years 2 months ago
1995
IEEE
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
RSP
2006
IEEE
15 years 4 months ago
2006
IEEE
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
SC
1992
ACM
15 years 2 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
DATE
2005
IEEE
15 years 4 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...