45 search results - page 4 / 9 » Performance Evaluation of Tiling for the Register Level |
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ISCA
1993
IEEE
15 years 2 months ago
1993
IEEE
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
SIES
2007
IEEE
15 years 4 months ago
2007
IEEE
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
SAMOS
2004
Springer
15 years 3 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
JUCS
2000
14 years 10 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
BILDMED
2008
15 years 18 hour ago
2008
Abstract. A key technique for protein analysis is the geometric alignment of 2D gel electrophoresis (2-DE) images. We introduce a new hybrid elastic registration approach for 2-DE ...