45 search results - page 5 / 9 » Performance Evaluation of Tiling for the Register Level |
FPL
2004
Springer
15 years 4 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
ICCAD
1998
IEEE
15 years 2 months ago
1998
IEEE
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
HPCA
1998
IEEE
15 years 2 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
MICRO
1998
IEEE
15 years 2 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
FMICS
2006
Springer
15 years 2 months ago
2006
Springer
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...