45 search results - page 6 / 9 » Performance Evaluation of Tiling for the Register Level |
SIGMETRICS
2006
ACM
15 years 4 months ago
2006
ACM
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
109
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BMCBI
2005
14 years 10 months ago
2005
Background: In two-channel competitive genomic hybridization microarray experiments, the ratio of the two fluorescent signal intensities at each spot on the microarray is commonly...
IPMI
2007
Springer
15 years 11 months ago
2007
Springer
The interest in registering a set of images has quickly risen in the field of medical image analysis. Mutual information (MI) based methods are well-established for pairwise regist...
113
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HPCA
2006
IEEE
15 years 11 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
ISCA
1996
IEEE
15 years 2 months ago
1996
IEEE
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...