45 search results - page 7 / 9 » Performance Evaluation of Tiling for the Register Level |
125
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GECCO
2004
Springer
15 years 7 months ago
2004
Springer
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
124
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CCECE
2006
IEEE
15 years 8 months ago
2006
IEEE
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator,...
84
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MASCOTS
2004
15 years 3 months ago
2004
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...
110
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GRID
2008
Springer
15 years 1 months ago
2008
Springer
The existence of good probabilistic models for the job arrival process and the delay components introduced at different stages of job processing in a Grid environment is important ...
155
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ISCA
2011
IEEE
14 years 5 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...