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» Performance Evaluation of View-Oriented Parallel Programming
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ICS
1999
Tsinghua U.
15 years 1 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
14 years 7 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ICS
2003
Tsinghua U.
15 years 2 months ago
Estimating cache misses and locality using stack distances
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
Calin Cascaval, David A. Padua
ALGORITHMICA
2002
120views more  ALGORITHMICA 2002»
14 years 9 months ago
An Experimental Study of Algorithms for Weighted Completion Time Scheduling
We consider the total weighted completion time scheduling problem for parallel identical machines and precedence constraints, P jprecj PwiCi. This important and broad class of pro...
Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenbe...
IISWC
2008
IEEE
15 years 3 months ago
STAMP: Stanford Transactional Applications for Multi-Processing
Abstract—Transactional Memory (TM) is emerging as a promising technology to simplify parallel programming. While several TM systems have been proposed in the research literature,...
Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, ...