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» Performance Evaluation of a Parallel Simulation Environment
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HPCA
2012
IEEE
13 years 7 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
INFOCOM
2006
IEEE
15 years 5 months ago
Mobile Emulab: A Robotic Wireless and Sensor Network Testbed
Abstract— Simulation has been the dominant research methodology in wireless and sensor networking. When mobility is added, real-world experimentation is especially rare. However,...
David Johnson, Tim Stack, Russ Fish, Daniel Montra...
GECCO
2006
Springer
147views Optimization» more  GECCO 2006»
15 years 3 months ago
Evolving a real-world vehicle warning system
Many serious automobile accidents could be avoided if drivers were warned of impending crashes before they occur. Creating such warning systems by hand, however, is a difficult an...
Nate Kohl, Kenneth O. Stanley, Risto Miikkulainen,...
105
Voted
ICS
2003
Tsinghua U.
15 years 5 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
CODES
2003
IEEE
15 years 5 months ago
A multiobjective optimization model for exploring multiprocessor mappings of process networks
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel