We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
This paper describes a novel negotiation protocol for cellular networks, which intelligently improves the performance of the network. Our proposed reactive mechanism enables the d...
Raz Lin, Daphna Dor-Shifer, Sarit Kraus, David Sar...
Understanding the dynamics of bodies of water and their impact on the global environment requires sensing information over the full volume of water. We develop a gradientbased dec...
Carrick Detweiler, Marek Doniec, Mingshun Jiang, M...
Wireless sensor networks have attracted attention from a diverse set of researchers, due to the unique combination of distributed, resource and data processing constraints. Howeve...
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...