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ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
15 years 9 months ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith
175
Voted
SIGMETRICS
1992
ACM
145views Hardware» more  SIGMETRICS 1992»
15 years 7 months ago
Analysis of the Generalized Clock Buffer Replacement Scheme for Database Transaction Processing
The CLOCK algorithm is a popular buffer replacement algorithm becauseof its simplicity and its ability to approximate the performance of the Least Recently Used (LRU) replacement ...
Victor F. Nicola, Asit Dan, Daniel M. Dias
LCN
2005
IEEE
15 years 9 months ago
Differentiation of Downlink 802.11e Traffic in the Virtual Collision Handler
— A number of analytical models have been proposed to describe the priority schemes of the Enhanced Distributed Channel Access (EDCA) mechanism of the IEEE 802.11e standard. EDCA...
Paal Engelstad, Olav N. Østerbø
GECCO
2005
Springer
124views Optimization» more  GECCO 2005»
15 years 9 months ago
Evolving petri nets to represent metabolic pathways
Given concentrations of metabolites over a sequence of time steps, the metabolic pathway prediction problem seeks a set of reactions and rate constants for them that could yield t...
Jeremiah Nummela, Bryant A. Julstrom
115
Voted
CHES
2006
Springer
111views Cryptology» more  CHES 2006»
15 years 7 months ago
Cache-Collision Timing Attacks Against AES
This paper describes several novel timing attacks against the common table-driven software implementation of the AES cipher. We define a general attack strategy using a simplified ...
Joseph Bonneau, Ilya Mironov