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DAC
2003
ACM
15 years 8 months ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich
110
Voted
IPPS
1997
IEEE
15 years 7 months ago
An Architecture Workbench for Multicomputers
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
Andy D. Pimentel, Louis O. Hertzberger
QEST
2006
IEEE
15 years 9 months ago
Load Balancing for Performance Differentiation in Dual-Priority Clustered Servers
Size-based policies have been known to successfully balance load and improve performance in homogeneous cluster environments where a dispatcher assigns a job to a server strictly ...
Ningfang Mi, Qi Zhang, Alma Riska, Evgenia Smirni
ITC
2000
IEEE
88views Hardware» more  ITC 2000»
15 years 7 months ago
Predicting device performance from pass/fail transient signal analysis data
Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, a technique based o...
James F. Plusquellic, Amy Germida, Jonathan Hudson...
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 9 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl