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185
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VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 7 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
COMCOM
2006
67views more  COMCOM 2006»
15 years 3 months ago
Performance analyses of three geography-based location strategies for PCS networks
Although many location schemes have been proposed and analyzed, the tradeoff among the location registration and the call delivery of different schemes and the relative performanc...
Wei Kuang Lai, Nian-Chin Wu
CCR
2006
148views more  CCR 2006»
15 years 3 months ago
NetScale: scalable time-stepped hybrid simulation of large IP networks
This paper presents a scalable time-stepped hybrid simulation algorithm which is well adapted to the simulation of large IP networks (up to one million of competing flows and netw...
Laurent Fournié, Dohy Hong, Florent Perisse
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
15 years 8 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...
137
Voted
SIGMETRICS
2004
ACM
127views Hardware» more  SIGMETRICS 2004»
15 years 8 months ago
Performance analysis of LAS-based scheduling disciplines in a packet switched network
The Least Attained Service (LAS) scheduling policy, when used for scheduling packets over the bottleneck link of an Internet path, can greatly reduce the average flow time for sh...
Idris A. Rai, Guillaume Urvoy-Keller, Mary K. Vern...